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Msr Class Reference

Public Types

enum  Register {
  IA32_TSC = 0x10 , IA32_PLATFORM_ID = 0x17 , IA32_APIC_BASE = 0x1b , IA32_FEATURE_CONTROL = 0x3a ,
  IA32_BIOS_SIGN_ID = 0x8b , IA32_SMM_MONITOR_CTL = 0x9b , IA32_MTRR_CAP = 0xfe , IA32_SYSENTER_CS = 0x174 ,
  IA32_SYSENTER_ESP = 0x175 , IA32_SYSENTER_EIP = 0x176 , IA32_THERM_INTERRUPT = 0x19b , IA32_THERM_STATUS = 0x19c ,
  IA32_MISC_ENABLE = 0x1a0 , IA32_FLEX_BRVID_SEL = 0x1a1 , IA32_DEBUG_CTL = 0x1d9 , IA32_MTRR_PHYS_BASE = 0x200 ,
  IA32_MTRR_PHYS_MASK = 0x201 , IA32_MTRR_FIX64K_BASE = 0x250 , IA32_MTRR_FIX16K_BASE = 0x258 , IA32_MTRR_FIX4K_BASE = 0x268 ,
  IA32_CR_PAT = 0x277 , IA32_MTRR_DEF_TYPE = 0x2ff , IA32_VMX_BASIC = 0x480 , IA32_VMX_CTRL_PIN = 0x481 ,
  IA32_VMX_CTRL_CPU0 = 0x482 , IA32_VMX_CTRL_EXIT = 0x483 , IA32_VMX_CTRL_ENTRY = 0x484 , IA32_VMX_CTRL_MISC = 0x485 ,
  IA32_VMX_CR0_FIXED0 = 0x486 , IA32_VMX_CR0_FIXED1 = 0x487 , IA32_VMX_CR4_FIXED0 = 0x488 , IA32_VMX_CR4_FIXED1 = 0x489 ,
  IA32_VMX_VMCS_ENUM = 0x48a , IA32_VMX_CTRL_CPU1 = 0x48b , IA32_VMX_EPT_VPID = 0x48c , IA32_VMX_TRUE_PIN = 0x48d ,
  IA32_VMX_TRUE_CPU0 = 0x48e , IA32_VMX_TRUE_EXIT = 0x48f , IA32_VMX_TRUE_ENTRY = 0x490 , IA32_DS_AREA = 0x600 ,
  IA32_EXT_XAPIC = 0x800 , IA32_EFER = 0xc0000080 , AMD_IPMR = 0xc0010055 , AMD_SVM_HSAVE_PA = 0xc0010117
}
enum  Feature_Control { FEATURE_LOCKED = 1ul << 0 , FEATURE_VMX_I_SMX = 1ul << 1 , FEATURE_VMX_O_SMX = 1ul << 2 }

Static Public Member Functions

template<typename T>
static ALWAYS_INLINE T read (Register msr)
template<typename T>
static ALWAYS_INLINE void write (Register msr, T val)

Member Enumeration Documentation

◆ Feature_Control

enum Msr::Feature_Control
82 {
83 FEATURE_LOCKED = 1ul << 0,
84 FEATURE_VMX_I_SMX = 1ul << 1,
85 FEATURE_VMX_O_SMX = 1ul << 2
86 };

◆ Register

enum Msr::Register
30 {
31 IA32_TSC = 0x10,
32 IA32_PLATFORM_ID = 0x17,
33 IA32_APIC_BASE = 0x1b,
34 IA32_FEATURE_CONTROL = 0x3a,
35 IA32_BIOS_SIGN_ID = 0x8b,
36 IA32_SMM_MONITOR_CTL = 0x9b,
37 IA32_MTRR_CAP = 0xfe,
38 IA32_SYSENTER_CS = 0x174,
39 IA32_SYSENTER_ESP = 0x175,
40 IA32_SYSENTER_EIP = 0x176,
41 IA32_THERM_INTERRUPT = 0x19b,
42 IA32_THERM_STATUS = 0x19c,
43 IA32_MISC_ENABLE = 0x1a0,
44 IA32_FLEX_BRVID_SEL = 0x1a1,
45 IA32_DEBUG_CTL = 0x1d9,
46 IA32_MTRR_PHYS_BASE = 0x200,
47 IA32_MTRR_PHYS_MASK = 0x201,
48 IA32_MTRR_FIX64K_BASE = 0x250,
49 IA32_MTRR_FIX16K_BASE = 0x258,
50 IA32_MTRR_FIX4K_BASE = 0x268,
51 IA32_CR_PAT = 0x277,
52 IA32_MTRR_DEF_TYPE = 0x2ff,
53
54 IA32_VMX_BASIC = 0x480,
55 IA32_VMX_CTRL_PIN = 0x481,
56 IA32_VMX_CTRL_CPU0 = 0x482,
57 IA32_VMX_CTRL_EXIT = 0x483,
58 IA32_VMX_CTRL_ENTRY = 0x484,
59 IA32_VMX_CTRL_MISC = 0x485,
60 IA32_VMX_CR0_FIXED0 = 0x486,
61 IA32_VMX_CR0_FIXED1 = 0x487,
62 IA32_VMX_CR4_FIXED0 = 0x488,
63 IA32_VMX_CR4_FIXED1 = 0x489,
64 IA32_VMX_VMCS_ENUM = 0x48a,
65 IA32_VMX_CTRL_CPU1 = 0x48b,
66 IA32_VMX_EPT_VPID = 0x48c,
67
68 IA32_VMX_TRUE_PIN = 0x48d,
69 IA32_VMX_TRUE_CPU0 = 0x48e,
70 IA32_VMX_TRUE_EXIT = 0x48f,
71 IA32_VMX_TRUE_ENTRY = 0x490,
72
73 IA32_DS_AREA = 0x600,
74 IA32_EXT_XAPIC = 0x800,
75 IA32_EFER = 0xc0000080,
76
77 AMD_IPMR = 0xc0010055,
78 AMD_SVM_HSAVE_PA = 0xc0010117,
79 };

Member Function Documentation

◆ read()

template<typename T>
ALWAYS_INLINE T Msr::read ( Register msr)
inlinestatic
91 {
92 mword h, l;
93 asm volatile ("rdmsr" : "=a" (l), "=d" (h) : "c" (msr));
94 return static_cast<T>(static_cast<uint64>(h) << 32 | l);
95 }

◆ write()

template<typename T>
ALWAYS_INLINE void Msr::write ( Register msr,
T val )
inlinestatic
100 {
101 asm volatile ("wrmsr" : : "a" (static_cast<mword>(val)), "d" (static_cast<mword>(static_cast<uint64>(val) >> 32)), "c" (msr));
102 }
The documentation for this class was generated from the following file:
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